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<!DOCTYPE ArticleSet PUBLIC "-//NLM//DTD PubMed 2.7//EN" "https://dtd.nlm.nih.gov/ncbi/pubmed/in/PubMed.dtd">
<ArticleSet>
<Article>
<Journal>
				<PublisherName>Tarbiat Modares University</PublisherName>
				<JournalTitle>The Modares Journal of Electrical Engineering</JournalTitle>
				<Issn>2228-527X</Issn>
				<Volume>12</Volume>
				<Issue>2</Issue>
				<PubDate PubStatus="epublish">
					<Year>2012</Year>
					<Month>07</Month>
					<Day>01</Day>
				</PubDate>
			</Journal>
<ArticleTitle>A High Dynamic Range Digitally-Controlled Oscillator (DCO) for All-Digital PLL Systems</ArticleTitle>
<VernacularTitle>•	اسیلاتور کنترل شونده‌ی دیجیتالی با محدوده‌ی فرکانسی گسترده برای حلقه های قفل فاز تمام دیجیتال</VernacularTitle>
			<FirstPage>16</FirstPage>
			<LastPage>21</LastPage>
			<ELocationID EIdType="pii">12889</ELocationID>
			
			
			<Language>EN</Language>
<AuthorList>
<Author>
					<FirstName>Samira</FirstName>
					<LastName>Jafarzade</LastName>
<Affiliation>Tarbiat Modares University, samira.</Affiliation>

</Author>
<Author>
					<FirstName>Abumoslem</FirstName>
					<LastName>Jannesari</LastName>
<Affiliation>Tarbiat Modares University,</Affiliation>

</Author>
</AuthorList>
				<PublicationType>Journal Article</PublicationType>
		<Abstract>&lt;span&gt;In this paper, a new high dynamic range Digitally-Controlled Oscillator (DCO) for All-DPLL systems is proposed. The proposed DCO is based on using a ΔΣ modulator as a Digital-to-Analog converter. Using ΔΣ DAC can provide a very high resolution (18-bit) control on the DCO. The ΔΣ DAC output is a 2-level pulse signal that needs to be filtered for cancelling the out of band shaped noise. The used ΔΣ modulator is a 4&lt;sup&gt;th&lt;/sup&gt; order MASH ΔΣ modulator working with the OSR of 128 and the sampling frequency of 450MHz. the proposed DCO is used in a PLL to synthesize the frequency in the range of 1700&lt;/span&gt;&lt;span&gt;MHz&lt;/span&gt;&lt;span&gt; to 1800MHz for GSM-1800 application. The achieved phase noise for this PLL based synthesizer in whole the range is -115 dBc/Hz at the offset frequency of 500 kHz. The designed ADPLL including the DCO is simulated in ADS with 0.18µm CMOS technology.&lt;/span&gt;</Abstract>
		<ObjectList>
			<Object Type="keyword">
			<Param Name="value">ADPLL</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">DCO</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">ΔΣ DAC</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">OSR</Param>
			</Object>
			<Object Type="keyword">
			<Param Name="value">phase noise</Param>
			</Object>
		</ObjectList>
<ArchiveCopySource DocType="pdf">https://mjee.modares.ac.ir/article_12889_b458201027eb55a7a6dcb41b0af61993.pdf</ArchiveCopySource>
</Article>
</ArticleSet>
