Volume 6, Issue 1 (2006)
MJEE 2006, 6(1): 75-84 |
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SEPYANI A, KABIR E, BEHAZIN F. DESIGNING A RECONFIGURABLE ACCELERATOR. MJEE 2006; 6 (1) :75-84
URL: http://mjee.modares.ac.ir/article-17-10012-en.html
URL: http://mjee.modares.ac.ir/article-17-10012-en.html
1- YMA research and industrial complex
2- TARBIAT MODARES UNIVERSITY
3- YAM research and industrial complex
2- TARBIAT MODARES UNIVERSITY
3- YAM research and industrial complex
Abstract: (3275 Views)
Many of the video processing algorithms cannot be implemented in real time on general computers, due to their computational complexity. For an efficient implementation, a custom hardware that can be reconfigured for the algorithm, is used. In this paper a new acceleration hardware based on FPGA elements is proposed. This hardware can be adapted with the processing algorithm through FPGA design reconfiguration. Using a PCI slot, this hardware communicates with a Pc. The FPGAs are programmed through the PCI slot. The video frames are supplied to this hardware for processing. The performance of this hardware is evaluated using warping algorithms. The first and second order warping for a 512*512 frame can be done in 7.9 ms.
Received: 2003/08/2 | Accepted: 2005/07/2 | Published: 2007/03/2
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